Sum addressed decoder

In CPU design, the use of a Sum Addressed Decoder or Sum Addressed Memory (SAM) Decoder is a method of reducing the latency of the CPU cache access. This is achieved by fusing the address generation sum operation with the decode operation in the cache SRAM. ==Overview== The L1 data cache should usually be in the most critical CPU resource, because...
Found on http://en.wikipedia.org/wiki/Sum_addressed_decoder
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